1. Field of the Invention
This invention relates to improvements in MOS transistors and methods for making same in digital BiCMOS processes, and more particularly to improvements in methods for making isolated, vertical PNP transistors in standard non-oxide-isolated digital BiCMOS twin well DUF (buried layer) processes.
2. Background Information
An accelerating trend in the integrated circuit industry is the merging of analog and digital functions onto the same semiconductor substrate. An example is the integration of analog functions into DSP or other large digital blocks to form complete systems. These so-called xe2x80x9cmixed-signalxe2x80x9d chips are increasingly built using digital BiCMOS technologies, for a variety of reasons. BiCMOS technologies generally provide optimized low-voltage logic performance, particularly in speed of operation. Most BiCMOS processes now have a variety of components available, which simplifies design. However, most designs are heavily weighted toward digital content.
Most digital BiCMOS processes are based on P type silicon substrates, with the backgates of the NMOS devices being interconnected through the common substrate. The lack of non-isolated NMOS transistors can result in several design problems for mixed-signal circuits. First, there is the confusion over substrate biasing when combining dual-supply analog functions with single-supply digital functions. Secondly, the injection of digital switching noise into sensitive analog nodes via the common substrate is undesirable.
Fully isolated NMOS devices have been demonstrated in analog BiCMOS or LinBiCMOS processes. Typically, however, in such processes, an N+ buried layer is used to form the vertical isolation region, while an annular N well or deep N+ collector region is used for the lateral isolation. An NMOS transistor can then be built in an isolated P type epitaxial layer or island. This technique, however, has drawbacks when used in digital BiCMOS processes. Normally, the epitaxial region is thin, on the order of 1.25 xcexcm, and does not allow sufficient vertical separation between the N+ DUF and the N+ source/drain regions. This may lead to severe punch-through breakdown problems under normal minimal bias.
Other processes for forming isolated NMOS devices have been proposed, as well. Some of such processes use deep N wells for high-voltage devices, but require relatively high temperature processing steps. Such high temperatures are incompatible with digital BiCMOS processes, since the N+ buried layer up-diffusion becomes excessive. This requires that the epitaxial layer be increased, thereby degrading the performance of critical NPN devices.
What is needed is a low-cost method for building isolated NMOS transistors in a digital BiCMOS process without disturbing the existing components. In addition to the ability to isolate a single NMOS transistor, there is also a need to isolate large blocks of digital circuitry without altering the design rules, since often it is necessary to bias the substrate below ground for analog functions.
In light of the above, therefore, it is an object of the invention to provide an improved isolated NMOS transistor and method for making it.
It is another object of the invention to provide an improved method for making an isolated NMOS transistor of the type described that can be fabricated in existing BiCMOS technologies with only few additional process steps.
It is another object of the invention to provide an improved method for making an isolated NMOS transistor of the type described that can be fabricated in existing BiCMOS technologies without altering the design rules and without reducing the quality or integrity of existing components.
It is another object of the invention to provide an improved method for making a BiCMOS circuit containing isolated NMOS transistor of the type described.
It is another object of the invention to provide an improved method for making a BiCMOS circuit in which single or selected individual isolated NMOS transistor of the type described can be fabricated.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.
According to a broad aspect of the invention, a method is presented for making an isolated NMOS transistor in a BiCMOS process. The method includes forming an Nxe2x88x92 conductivity type DUF layer in a P conductivity type semiconductor substrate. Alternate contiguous N+ and P conductivity type buried regions are then formed in the substrate on the Nxe2x88x92 conductivity type DUF layer, and alternate contiguous N and P conductivity well regions are formed respectively above and in contact with the N+ and P conductivity type buried regions. Then, NMOS transistor source and drain regions are formed in at least one of the P conductivity type well regions.
According to another broad aspect of the invention, another method for making an isolated NMOS transistor in a BiCMOS process is presented. The method includes forming an Nxe2x88x92 conductivity type DUF layer in a P conductivity type semiconductor substrate followed by forming alternate contiguous N+ and P conductivity type buried regions in the substrate. A layer of substantially intrinsic semiconductor material is then formed on the substrate in which alternate and contiguous N and P conductivity type wells are formed, respectively above and extending to the N+ and P conductivity type buried regions. Finally, NMOS source and drain regions are formed in at least one of the P conductivity type wells.
The method is preferably performed concurrently with the construction of a bipolar transistor structure elsewhere on the substrate. More particularly, the steps of forming the P conductivity type buried layer may be performed as a part of a simultaneous formation of a collector element of a PNP transistor elsewhere on the substrate.
According to another broad aspect of the invention, a method for making an isolated NMOS transistor is presented. The method includes forming a first layer of oxide on a P conductivity type substrate, and patterning the layer of oxide to define an opening through which an Nxe2x88x92 conductivity type region is formed in the substrate. A second layer of oxide is then formed and patterned on the substrate to provide an opening exposing the Nxe2x88x92 conductivity type region and the substrate through which an N+ conductivity type region is formed in the Nxe2x88x92 conductivity type region and the substrate. The second layer of oxide is stripped from the substrate, and a third layer of oxide formed overall through which an acceptor impurity is introduced overall into the substrate at a level at which the acceptor impurity is bounded by the N+ conductivity type region. After the third layer of oxide is stripped, a layer of silicon is formed overall on the substrate in which alternate N and P conductivity type wells are formed. The alternate N and P conductivity type wells extend from the surface to contact the Nxe2x88x92 conductivity type region and the substrate. Finally, NMOS source and drain regions are formed in one of the P conductivity type wells.
According to yet another broad aspect of the invention, an isolated NMOS transistor is presented. The isolated NMOS transistor has a semiconductor substrate having an N conductivity type DUF region under a series of contiguous alternate N and P conductivity type buried layers. A series of N+ and P conductivity type wells extend from a surface of the substrate to contact respective ones of the N conductivity type and P conductivity type buried layers, whereby a P conductivity type well region is isolated from the substrate by the N conductivity type DUF region, the N conductivity type buried layers, and the N+ conductivity type wells. The isolated P conductivity type contains source and drain regions for the final NMOS transistor.